A prior art is hereinafter described with reference to FIGS. 1A through 1C.
First, a polycrystalline silicon film 13 is grown to a predetermined thickness on a silicon oxide film 2 formed on the principal surface of a silicon substrate 1, an impurity is introduced by ion implantation, and a heat treatment is effected for activation (FIG. 1A). Next, the polycrystalline silicon film 13 is patterned in the form of a resistance element 15 (FIG. 1B). After the resistance element 15 is covered with an interlayer insulating film 14, an electrode line 6 made of a metal such as A1 or the like is connected to a contact portion of the resistance element 15 through a contact hole formed through the interlayer insulating film 14 (FIG. 1C).
In the resistance element using such a thin film polycrystalline silicon film, temperature dependence of the conductivity of the polycrystalline silicon is determined by the height of a potential barrier beyond which the carrier goes at a grain boundary. If the impurity density within the grain is lowered, then the potential barrier becomes high and, if the temperature is elevated, then the conductivity becomes large. That is, the smaller the polycrystalline silicon is in the impurity density, the greater negative temperature coefficient (the higher the temperature is, the lower the resistance value becomes) it acquires.
If such a polycrystalline silicon resistance element having a greater negative temperature coefficient is used, for example, within a bipolar memory of a great power consumption, it does not only pose a constraint on the design of operating point, but also causes thermal run-away. Therefore, it is important to reduce the temperature coefficient of the resistance element.
As one of the measures for reducing the temperature coefficient of the resistance value, there is one in which when the resistance element is formed in the predetermined planar form, the thickness of the polycrystalline silicon film is thinned to increase the impurity density.
In FIGS. 1A through 1C, in order to thin the film thickness, it is necessary to lower an accelerating voltage of the ion implantation while increasing the amount of dosed ion. That is, it is necessary to lower the accelerating voltage so that even if the film thickness is thinned the ion may not penetrate the polycrystalline silicon film. However, if the accelerating voltage is lowered, then it becomes difficult to focus the beam, and the dispersion of energy becomes great. In the state-of-the-art equipment, 10 keV poses a lower minimum limit to the accelerating voltage, which cannot be sufficiently lowered.
Further, if the amount of dosed ion is increased, then a period of time during which the ion is implanted becomes long.
If, in order to reduce the dispersion of energy with the amount of dosed ion kept constant, only the accelerating voltage is increased, then the peak of the impurity density will come outside of the polycrystalline silicon film, and the impurity density within the polycrystalline silicon film will be lowered. Therefore, in order to increase the accelerating voltage to obtain the same impurity density within the polycrystalline silicon film, it is necessary to further increase the amount of dosed ion, which further increases the period of time during which the ion is implanted.
On the other hand, when the insulating film is formed on the polycrystalline silicon film and thereafter the ion is implanted, since the accelerating voltage is increased, the energy dispersion becomes small. However, in this case, since the impurity is also implanted into the insulating film, a large amount of dosed ion also becomes necessary until the impurity is added by an amount needed for the polycrystalline silicon film, and it takes a long time to implant the ion.
As shown in FIG. 2, when the density of the impurity (boron) within the polycrystalline silicon film is 1.times.10.sup.19 atoms/cm.sup.3, since the temperature coefficient (change rate of the resistance value per 1 degree Centigrade) becomes below 3000 ppm, which corresponds to about a half of the temperature coefficient for the case in which it is 1.times.10.sup.18 atoms/cm.sup.3, it is free in practice of any problem. Therefore, it is preferable to set the impurity density of the polycrystalline silicon forming the resistance element to above 1.times.10.sup.19 atoms/cm.sup.3.
In order to obtain the impurity density of 1.times.10.sup.19 atoms/cm.sup.3 for the polycrystalline silicon film according to the ion implantation process, it is necessary to lower the accelerating voltage, but as described above, according to the state-of-the-art equipment, 10 keV is the lower minimum limit and yet, with this 10 keV, the dispersion or variation of the impurity density becomes .+-.60%, and no practical resistance element can be obtained. The lower limit of the variation of the impurity density, from the practical point of view, is .+-.30%, but to this end, it is necessary to set the accelerating voltage to 15 keV. However, in order to set the impurity density of the polycrystalline silicon film to 1.times.10.sup.19 atoms/cm.sup.3 or above under this condition, it is necessary to set the peak impurity density within the polycrystalline silicon film to 1.times.10.sup.20 atoms/cm.sup.3 or above and to make this peak impurity density lie within the polycrystalline silicon film. In order to satisfy these conditions, the thickness of the polycrystalline silicon film need to be greater than 100 nm (preferably greater than 120 nm), and the thickness of below 100 nm cannot meet the foregoing conditions.
As described above, in order to reduce the temperature coefficient of the resistance element, it is necessary to set the impurity density to above 1.times.10.sup.19 atoms/cm.sup.3, and if the thickness of the polycrystalline silicon film is correspondingly set to below 100 nm in order to obtain the same sheet resistance as when the low impurity density is used, then the ion implantation technique cannot be used.
Further, when a thin polycrystalline silicon film is used, if in order to reduce the variation of the impurity density the accelerating voltage is increased, then the ion penetrates not only the polycrystalline silicon film, but also the insulating film therebelow, forming an undesired impurity area at the silicon substrate therebelow. Therefore, it becomes practically impossible to set the thickness of the insulating film which lies below the polycrystalline silicon film to below 300 nm, which poses a constraint on thinning the insulating film in order to improve the diffusion of the heat which is generated at the resistance element.